RTL / SystemVerilog
Content-Addressable Memory
A synthesizable 4-entry, 32-bit memory built for parallel lookup.
Overview
The design stores four 32-bit words and compares a search value against every valid entry at the same time. It reports both match and miss conditions.
Architecture
Synchronous writes update the selected entry and its valid bit. Combinational lookup checks the search value against all valid entries in parallel.
WriteValidateSearchMatch
Verification
A self-checking SystemVerilog testbench covered writes, valid-bit behavior, successful lookups, and misses. All 10 functional tests passed.